MIPI Screen
- Configure PAD to TTL mode
# vi infinity2m-ssc011a-s01a-padmux-display_for_mipi.dtsi
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License version 2 for more details.
*
*/
#include <../../../../drivers/sstar/include/infinity2m/padmux.h>
#include <../../../../drivers/sstar/include/mdrv_puse.h>
/ {
soc {
padmux {
compatible = "sstar-padmux";
schematic =
//<PAD_GPIO0 >,
<PAD_GPIO1 PINMUX_FOR_GPIO_MODE MDRV_PUSE_I2C1_DEV_RESET >,
<PAD_GPIO2 PINMUX_FOR_I2C1_MODE_1 MDRV_PUSE_I2C1_SCL >,
<PAD_GPIO3 PINMUX_FOR_I2C1_MODE_1 MDRV_PUSE_I2C1_SDA >,
<PAD_GPIO4 PINMUX_FOR_PWM0_MODE_3 MDRV_PUSE_PWM0 >,
<PAD_GPIO5 PINMUX_FOR_PWM1_MODE_4 MDRV_PUSE_PWM1 >,
<PAD_GPIO6 PINMUX_FOR_EJ_MODE_3 MDRV_PUSE_EJ_TDO >,
<PAD_GPIO7 PINMUX_FOR_EJ_MODE_3 MDRV_PUSE_EJ_TDI >,
//<PAD_GPIO8 >,
//<PAD_GPIO9 >,
//<PAD_GPIO10 >,
<PAD_GPIO11 PINMUX_FOR_GPIO_MODE MDRV_PUSE_I2CSW_SCL>,
<PAD_GPIO12 PINMUX_FOR_GPIO_MODE MDRV_PUSE_I2CSW_SDA>,
<PAD_GPIO13 PINMUX_FOR_GPIO_MODE MDRV_PUSE_I2C1_DEV_IRQ >,
//<PAD_GPIO14 >,
//<PAD_FUART_RX >,
//<PAD_FUART_TX PINMUX_FOR_GPIO_MODE MDRV_PUSE_UTMI_POWER>,
<PAD_FUART_CTS PINMUX_FOR_GPIO_MODE MDRV_PUSE_CPUFREQ_VID0>,
<PAD_FUART_RTS PINMUX_FOR_GPIO_MODE MDRV_PUSE_CPUFREQ_VID1>,
//<PAD_TTL0 PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_PWR >,
<PAD_TTL6 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_P_CH0 >,
<PAD_TTL7 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_N_CH0>,
<PAD_TTL8 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_P_CH1>,
<PAD_TTL9 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_N_CH1 >,
<PAD_TTL10 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_P_CH2 >,
<PAD_TTL11 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_N_CH2 >,
<PAD_TTL12 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_P_CH3 >,
<PAD_TTL13 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_N_CH3 >,
<PAD_TTL14 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_P_CH4 >,
<PAD_TTL15 PINMUX_FOR_TX_MIPI_MODE_1 MDRV_PUSE_TX_MIPI_N_CH4 >,
<PAD_UART0_RX PINMUX_FOR_UART0_MODE_1 MDRV_PUSE_UART0_RX >,
<PAD_UART0_TX PINMUX_FOR_UART0_MODE_1 MDRV_PUSE_UART0_TX >,
//<PAD_UART1_RX >,
//<PAD_UART1_TX >,
//<PAD_SD_CLK PINMUX_FOR_I2S_MODE_3 MDRV_PUSE_I2S_BCK >,
<PAD_SD_CLK PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_CLK >,
//<PAD_SD_CMD PINMUX_FOR_I2S_MODE_3 MDRV_PUSE_I2S_SDI >,
<PAD_SD_CMD PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_CMD >,
//<PAD_SD_D0 PINMUX_FOR_I2S_MODE_3 MDRV_PUSE_I2S_WCK >,
<PAD_SD_D0 PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_D0 >,
<PAD_SD_D1 PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_D1>,
<PAD_SD_D2 PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_D2>,
//<PAD_SD_D3 PINMUX_FOR_I2S_MODE_3 MDRV_PUSE_I2S_SDO >,
<PAD_SD_D3 PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_D3>,
<PAD_PM_SD_CDZ PINMUX_FOR_SDIO_MODE_1 MDRV_PUSE_SDIO0_CDZ>,
<PAD_PM_IRIN PINMUX_FOR_PM_IRIN_MODE MDRV_PUSE_IR>, // IR: default non-GPIO
//<PAD_PM_SPI_CZ >, // default not-GPIO
//<PAD_PM_SPI_CK >, // default not-GPIO
//<PAD_PM_SPI_DI >, // default not-GPIO
//<PAD_PM_SPI_DO >, // default not-GPIO
//<PAD_PM_SPI_WPZ >, // default not-GPIO
//<PAD_PM_SPI_HLD >, // default not-GPIO
//<PAD_PM_LED0 >,
//<PAD_PM_LED1 >,
<PAD_SAR_GPIO0 PINMUX_FOR_SAR_MODE MDRV_PUSE_SAR_GPIO0 >, // sar: default not-GPIO,
//<PAD_SAR_GPIO1 >, // sar: default not-GPIO
//<PAD_SAR_GPIO2 >, // sar: default not-GPIO
//<PAD_ETH_RN >, // ETH: default not-GPIO
//<PAD_ETH_RP >, // ETH: default not-GPIO
//<PAD_ETH_TN >, // ETH: default not-GPIO
//<PAD_ETH_TP >, // ETH: default not-GPIO
<PAD_DM_P1 PINMUX_FOR_USB_MODE MDRV_PUSE_UTMI1_DM >, // utmi: default not-GPIO
<PAD_DP_P1 PINMUX_FOR_USB_MODE MDRV_PUSE_UTMI1_DP >, // utmi: default not-GPIO
<PAD_DM_P2 PINMUX_FOR_USB_MODE MDRV_PUSE_UTMI2_DM >, // utmi: default not-GPIO
<PAD_DP_P2 PINMUX_FOR_USB_MODE MDRV_PUSE_UTMI2_DP >, // utmi: default not-GPIO
//<PAD_HSYNC_OUT >,
//<PAD_VSYNC_OUT >,
<PAD_HDMITX_SCL PINMUX_FOR_DMIC_MODE_2 MDRV_PUSE_DMIC_D1 >,
<PAD_HDMITX_SDA PINMUX_FOR_DMIC_MODE_2 MDRV_PUSE_DMIC_D0 >,
<PAD_HDMITX_HPD PINMUX_FOR_DMIC_MODE_2 MDRV_PUSE_DMIC_CLK >,
<PAD_HSYNC_OUT PINMUX_FOR_IDAC_MODE MDRV_PUSE_IDAC_HSYNC>,
<PAD_VSYNC_OUT PINMUX_FOR_IDAC_MODE MDRV_PUSE_IDAC_VSYNC>;
//<PAD_SATA_GPIO >;
status = "ok"; // ok or disable
//status = "disable";
};
};
};Obtain the schedule from the data book on the screen
Modify screen parameters
You can capy JpegPlayer/EK79007_1024x600_MIPI.h, Based on it, the modification method is the same as TTL screen.Modify the value of swap
(MI_PANEL_ChannelSwapType_e)2,
(MI_PANEL_ChannelSwapType_e)4,
(MI_PANEL_ChannelSwapType_e)3,
(MI_PANEL_ChannelSwapType_e)1,
(MI_PANEL_ChannelSwapType_e)0,
The default PAD pin and Mipi correspond to the following functions:
If the actual circuit connection is inconsistent, you need to modify the value of channelswap:
The revised rules are as follows:
Firstly, pad and lane were grouped:
And understand the meaning of ech0-4
Here is an example. D0-d3 is respectively connected to the d0-d3 of the screen, and CK is connected to the ck of the screen. Therefore, the following table is obtained:
Modify the initialization array according to the initialization code provided by the screen manufacturer
Modify the value of stmipidsiconfig
MI_PANEL_MipiDsiConfig_t stMipiDsiConfig =
{
//HsTrail HsPrpr HsZero ClkHsPrpr ClkHsExit ClkTrail ClkZero ClkHsPost DaHsExit ContDet
5, 3, 5, 10, 14, 3, 12, 10, 5, 0,
//Lpx TaGet TaSure TaGo
16, 26, 24, 50,
//Hac, Hpw, Hbp, Hfp, Vac, Vpw, Vbp, Vfp, Bllp, Fps
1024, 5, 50, 23, 600, 1, 23, 12, 0, 60,
E_MI_PNL_MIPI_DSI_LANE_4, // MIPnlMipiDsiLaneMode_e enLaneNum;
E_MI_PNL_MIPI_DSI_RGB888, // MIPnlMipiDsiFormat_e enFormat;
E_MI_PNL_MIPI_DSI_SYNC_PULSE, // MIPnlMipiDsiCtrlMode_e enCtrl;
EK79007_INIT_CMD,
sizeof(EK79007_INIT_CMD),
1, 0x01AF, 0x01B9, 0x80D2, 7,
2,2,2,2,2,
};
文档更新时间: 2021-03-23 14:11 作者：Aeeditor
